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(R)
ISL59920
Data Sheet December 19, 2008 FN6826.0
Triple Analog Video Delay Line
The ISL59920 ia a triple analog delay line that provides skew compensation between three high-speed signals. These parts are ideal for compensating for the skew introduced by a typical CAT-5 cable (with differing electrical lengths on each twisted pair) when transmitting analog video. Using a simple serial interface, the ISL59920's delay is programmable in steps of 2ns up to a total delay of 62ns on each channel. The gain of the video amplifiers can be set to x1 (0dB) or x2 (6dB) for back-termination. The delay lines require a 5V supply.
Features
* 62ns total delay * 2.0ns delay step increments * Very low offset voltage * Drop-in compatible with the EL9115 * Low power consumption * Pb-free RoHS compliant 20 Ld QFN package
Applications
* Skew control for RGB video signals * Generating programmable high-speed analog delays
Pinout
ISL59920 (20 LD 5X5 QFN) TOP VIEW
18 TESTG 19 TESTR 17 TESTB 16 VSPO 15 ROUT 14 GNDO THERMAL PAD 13 GOUT 12 VSMO 11 BOUT CENABLE 7 SENABLE 8 SCLOCK 10 BIN 6 SDATA 9
VSP 1 RIN 2 GND 3 GIN 4 VSM 5
Ordering Information
PART NUMBER ISL59920IRZ ISL59920IRZ-T7* PART MARKING 59920IRZ 59920IRZ DELAY STEP SIZE (ns) MAX DELAY (ns) 62 62 2.0 2.0 TYPICAL POWER DISSIPATION 645mW 645mW PACKAGE 20 Ld 5mm x 5mm QFN 20 Ld 5mm x 5mm QFN PKG. DWG. # L20.5x5C L20.5x5C
*Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
20 X2
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2008. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL59920
Absolute Maximum Ratings (TA = +25C)
Supply Voltage (VS+ to VS-) . . . . . . . . . . . . . . . . . . . . . . . . . . . .12V Maximum Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . 60mA Storage Temperature Range . . . . . . . . . . . . . . . . . .-65C to +150C ESD Classification Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3000V Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300V Charged Device Model . . . . . . . . . . . . . . . . . . . . . . . . . . . .1200V
Thermal Information
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +135C Ambient Operating Temperature . . . . . . . . . . . . . . . .-40C to +85C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER dt tMAX DELDT tPD BW -3dB BW 0.1dB SR tR - t F VOVER Glitch THD X VN G_0 G_m G_f DG_m0 DG_f0 DG_fm VIN IB VOS ZOUT
VSP = VSPO = +5V, VSM = VSMP = -5V, GAIN = 2, TA = +25C, exposed die plate = -5V, x2 = 5V, RLOAD = 150 on all video outputs, unless otherwise specified. CONDITION MIN 1.8 55 TYP 2.1 63 1.6 Measured input to output, delay setting = 0ns Delay = 0ns Delay = 0ns 0ns Delay Time 20% to 80%, for any delay, 1V step for any delay, response to 1V step input Output settling time from last SCLK edge 1VP-P 10MHz sinewave, offset by +0.2V at mid delay setting Stimulate G, measure R/B at 1MHz Bandwidth = 150MHz 1.74 1.67 1.6 -8 -12 -10 Gain remains > 90% of nominal, Gain = 2 -0.7 3 Post offset calibration (Note 2), Delay = 0ns and Delay = Full -25 4.5 Chip enable = 0V 6 -4 5.4 8 -42 -58 10 load, 0.5V drive Switch high threshold 43 53 -29 -46 70 1.6 11 153 50 450 2.6 4 100 -43 -80 2 1.8 1.8 1.8 0.6 -1.8 -1.7 1.92 1.97 2 7.5 10 7.5 1.1 8 +20 6.3 -38 -63 MAX 2.5 68 UNIT ns ns ns ns MHz MHz V/s ns % ns dB dB mVRMS V/V V/V V/V % % % V A mV M dB dB mA V
DESCRIPTION Delay Increment Maximum Delay Delay Difference Between Channels for Same Delay Settings On All Channels Propagation Delay 3dB Bandwidth, 0ns Delay Time 0.1dB Bandwidth, 0ns Delay Time Slew Rate Transient Response Time Voltage Overshoot Switching Glitch Total Harmonic Distortion Crosstalk Output Noise Gain Zero Delay Gain Mid Delay Gain Full Delay Difference in Gain, 0 to Mid Difference in Gain, 0 to Full Difference in Gain, Mid to Full Input Voltage Range RIN, GIN, BIN Input Bias Current Output Offset Voltage Output Impedance
+PSRR -PSRR IOUT VIH
Rejection of Positive Supply Rejection of Negative Supply Output Drive Current Logic High
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ISL59920
Electrical Specifications
PARAMETER VIL Logic Low VSP = VSPO = +5V, VSM = VSMP = -5V, GAIN = 2, TA = +25C, exposed die plate = -5V, x2 = 5V, RLOAD = 150 on all video outputs, unless otherwise specified. (Continued) CONDITION Switch low threshold MIN 0.8 TYP MAX UNIT V
DESCRIPTION
POWER SUPPLY CHARACTERISTICS V+ VISP ISPO ISM ISMO
ISP
VSP, VSPO Positive Supply Range VSM, VSMO Negative Supply Range Positive Supply Current (Note 1) Positive Output Supply Current (Note 1) Negative Supply Current (Note 1) Negative Output Supply Current (Note 1) Supply Current (Note 1) Increase in ISP per unit step in delay per channel
+4.5 -4.5 98 11.3 -35.45 -15 115 13 -31 -13 0.9 2.6
+5.5 -5.5 127 15.3 -26 -11
V V mA mA mA mA mA mA
ISTANDBY
Positive Supply Standby Current (Note 1) Chip enable = 0V
SERIAL INTERFACE CHARACTERISTICS tMAX tSEN_SETUP Max SCLOCK Frequency Maximum programming clock speed 10 10 MHz ns
SENABLE to SCLOCK falling edge setup SENABLE falling edge should occur at least time. See Figure 14. tSEN_SETUP ns after previous (ignored) clock and tSEN_SETUP before next (desired) clock. Clock edges occurring within t_en_ck of the SENABLE falling edge will have indeterminate effect. Minimum Separation Between SENABLE If SENABLE is taken low less than 3s after rising edge and next SENABLE falling it was taken high, there is a small possibility that an offset correction will not be initiated. edge. See Figure 14. 3
tSEN_CYCLE
s
NOTE: 1. All supply currents measured with Delay R = 0ns, G = mid delay, B = full delay. 2. Offset measurements are referred to 75 load as shown in Figure 1.
75 VIN x2 VOUT VOS
75
FIGURE 1. VOS MEASUREMENT CONDITIONS
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FN6826.0 December 19, 2008
ISL59920 Pin Descriptions
PIN NUMBER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Thermal Pad PIN NAME VSP RIN GND GIN VSM BIN CENABLE SENABLE SDATA SCLOCK BOUT VSMO GOUT GNDO ROUT VSPO TESTB TESTG TESTR X2 PIN DESCRIPTION +5V for delay circuitry and input amp Red channel video input 0V for delay circuitry supply Green channel video input -5V for input amp Blue channel video input Chip Enable input, active high: logical high enables chip, low disables chip Serial Enable input, active low: logical low enables serial communication Serial Data input, logic threshold 1.2V: data to be programmed into chip Serial Clock input: Clock to enter data; logical; data written on negative edge Blue channel video output -5V for video output buffers Green channel video output 0V reference for input and output buffers Red channel video output +5V for video output buffers Blue channel phase detector output Green channel phase detector output Red channel phase detector output Gain Select Input: logical high = 2x (+6dB), logical low = 1x (0dB) Tie to -5V copper plane (inner or bottom layer) for best thermal conductivity. Use many vias to minimize thermal resistance between thermal pad and copper plane. Do not connect to GND - connection to GND is equivalent to shorting the -5V and GND planes together.
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FN6826.0 December 19, 2008
ISL59920 Typical Performance Curves
2 1 0 -1 -2 -3 -4 -5 -6 -7 VIN = 700mVP-P -8 GAIN = 1 -9 -10 100k 1M 0ns 20ns 40ns 30ns 50ns 62ns 2 1 0 -1 -2 -3 -4 -5 -6 -7 -8 VIN = 700mVP-P -9 GAIN = 2 -10 100k 1M 0ns 20ns 40ns 30ns 50ns 62ns
NORMALIZED GAIN (dB)
10ns
NORMALIZED GAIN (dB)
10ns
10M FREQUENCY (Hz)
100M
1G
10M FREQUENCY (Hz)
100M
1G
FIGURE 2. FREQUENCY RESPONSE (GAIN = 1)
FIGURE 3. FREQUENCY RESPONSE (GAIN = 2)
250
200 SPECTRUM (nV/Hz) SENABLE TIMEBASE: 500ns/div SENABLE: 1V/div OUTPUT: 100mV/div GAIN: 1
150
100
50
OUTPUT 0 0
100M
200M
300M
400M
500M
FREQUENCY (Hz)
FIGURE 4. OFFSET CORRECTION DAC ADJUST
FIGURE 5. NOISE SPECTRUM (10k TO 500MHz)
3.0 2.5 RISE/FALL TIME (ns) 2.0 1.5 1.0 0.5 0 0 FALL RISE RISE/FALL TIME (ns)
3.0 2.5 2.0 1.5 1.0 0.5 0 0 FALL RISE
4
8
12 16 20 24 28 32 36 40 44 48 52 56 60 DELAY (ns)
4
8
12 16 20 24 28 32 36 40 44 48 52 56 60 DELAY (ns)
FIGURE 6. RISE/FALL TIME vs DELAY TIME (GAIN = 1)
FIGURE 7. RISE/FALL TIME vs DELAY TIME (GAIN = 2)
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FN6826.0 December 19, 2008
ISL59920 Typical Performance Curves (Continued)
HARMONIC DISTORTION (dBc) -10 -20 -30 -40 -50 -60 -70 -80 2M 6M 10M 2ND HD 3RD HD V+ = +5.0V, V- = -5.0V VOUT = 1.0VP-P, SINE WAVE RL = 150 GAIN = 2 POSITIVE SUPPLY CURRENT (mA) 0 180 160 140 120 100 2 CHANNELS 80 GAIN = 2 60 0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 DELAY (ns) 1 CHANNEL 3 CHANNELS
14M
18M 22M 26M FREQUENCY (Hz)
30M
34M
38M
FIGURE 8. HARMONIC DISTORTION vs FREQUENCY
FIGURE 9. POSITIVE SUPPLY CURRENT (VSP) vs DELAY TIME
NEGATIVE SUPPLY CURRENT (mA)
200 SUPPLY CURRENT (mA) 180 DELAY = 62ns 160 140 120 DELAY = 0ns 100 80 GAIN = 1 OR 2 60 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 5.8 6.0
-42.5 -43.0 -43.5 -44.0 -44.5 -4.0 -45.5 -46.0 -46.5 -4.0 -4.2 -4.4 -4.6 -4.8 -5.0 -5.2 -5.4 SUPPLY VOLTAGE (V) -5.6 -5.8 -6.0 DELAY = 0ns DELAY = 62ns GAIN = 1 OR 2
SUPPLY VOLTAGE (V)
FIGURE 10. ISUPPLY+ vs VSUPPLY+
FIGURE 11. ISUPPLY- vs VSUPPLY-
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD - QFN EXPOSED DIEPAD SOLDERED TO PCB PER JESD51-5 4.5 4.0 POWER DISSIPATION (W) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (C) 3.54W
QF N 1
JA
=3
20 C/ W
FIGURE 12. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
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FN6826.0 December 19, 2008
ISL59920
1 VSP 19 TESTR 17 TESTB 18 TESTG 16 VSPO CENABLE 7
2
RIN
+
DELAY LINE + ROUT 15
4
GIN
+
DELAY LINE + GOUT 13
6
BIN
+
DELAY LINE + BOUT 11 X2 20 CONTROL LOGIC VSMO 12
9 10 8
SDATA SCLOCK SENABLE GND VSM [BOTTOM PLATE] C GND 14
3
5
FIGURE 13. ISL59920 BLOCK DIAGRAM
Applications Information
The ISL59920 is a triple analog delay line that provides skew compensation between three high-speed signals. This device compensates for time skew introduced by a typical CAT-5 cable with differing electrical lengths (due to different twist ratios) on each pair. The device can be programmed, via its SPI interface, to independently compensate for the three different cable delays while maintaining 120MHz bandwidth at its maximum setting.
TABLE 1. PART NUMBER ISL59920 MAX DELAY (ns) 62 DELAY INCREMENT (ns) 2.0
Serial Bus Operation
The ISL59920 is programmed via 8 bit words sent through its serial interface. The first bit (MSB) of SDATA is latched on the first falling clock edge after SENABLE goes low, as shown in Figure 14. This bit should be a 0 under all conditions except one (described in the subsequent Offset Compensation section). The next two bits determine the color register to be written to: 01 = R, 02 = G, and 03 = B (00 is reserved for test use). The final five bits set the delay for the specified color. After 8 bits are latched, any additional clocks are treated as a new word (data is shifted directly to the final registers as it is clocked in). This allows the user to write (for example) the 24 bits of data necessary for R, G, and B as a single 24 bit word. It is the user's responsibility to send complete multiples of 8 clock cycles. The serial state machine is reset on the falling edge of SENABLE, so any data corruption that may have occurred due to too many or two few clocks can be corrected with a new word with the correct number of clocks. The initial value of all registers on power-up is 0.
Figure 13 shows the ISL59920 block diagram. The 3 analog inputs are ground referenced single-ended signals. After the signal is received, the delay is introduced by switching filter blocks into the signal path. Each filter block is an all-pass filter introducing 2ns delay. In addition to adding delay, each filter block also introduces some low pass filtering. As a result, the bandwidth of the signal path decreases from 150MHz at 0ns delay setting to 120MHz at the maximum delay setting, as shown in Figures 2 and 3 of the "Typical Performance Curves" on page 5. In operation, it is best to allocate the most delayed signal 0ns delay then increase the delay on the other channels to bring them into line. This will result in delay compensation with the lowest power and distortion.
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ISL59920
SENABLE tSEN_SETUP SCLOCK tSEN_CYCLE
SDATA
0*
A1 a
A0 b
D4 v
D3 w
D2 x
D1 y
D0 z
*Except in system offset cal mode
FIGURE 14. SERIAL TIMING
TABLE 2. SERIAL BUS DATA vwxyz 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 ISL59920 DELAY 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 vwxyz 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 ISL59920 DELAY 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62
rising edge of the SENABLE pin after writing a delay word to any of the 3 channels. The offset calibration starts about 500ns after the SENABLE rising edge to allow the ISL59920 time to settle (electrically and thermally) to the new delay setting. It lasts about 2.5s, for a total offset correction time of 3.0s. During calibration, the ISL59920's inputs are internally shorted together (however the characteristics of the ISL59920's differential input pins stay the same), and the offset of the output stage is adjusted until it has been minimized. In addition to automatically after a delay change (or any register write), an additional offset calibration may be initiated at any time, such as: * When the die temperature changes. Applying power to the ISL59920 will cause the die temperature to quickly increase then slowly settle over 20 to 30 seconds. Because the ISL59920 powers-down unused delay stages (to minimize power consumption), the die temp will also change and settle after a delay change. Initiating an offset 20 seconds (or longer, depending on the thermal characteristics of the system) after power-on or a delay change will minimize the offset in normal operation thereafter. * When the ambient temperature changes. If you are monitoring the temperature, initiate a calibration every time the temperature shifts by 5 to 10 degrees. If you are not monitoring temperature, initiate a calibration periodically, as expected by the environment the device is in. * After a CENABLE (Chip Enable) cycle. The CENABLE pin may be taken low to put the ISL59920 in a low power standby mode to conserve power when not needed. When the CENABLE pin goes high to exit this low power mode, the ISL59920 will recall the delay settings but it will not recall the correct offset calibration settings, so to maintain low offset, a write to the delay register is required after a CENABLE cycle. Offset errors may be as large as 200mV coming out of standby mode - recalibration is a necessity. For best performance, initiate an additional
NOTE: Delay register word = 0abvwxyz; Red register - ab = 01; Green register - ab = 10; Blue register - ab = 11; vwxyz selects delay.
Offset Compensation
Each delay stage of the ISL59920 contributes a small amount of offset to the signal. At the max delay of 31 stages, the magnitude of that offset may be 100mV or more. In addition, the offset voltage may have a temperature coefficient, so that temperature variations can cause the offset to drift from its nominal value. The power consumption (and thus the die temperature) of the ISL59920 itself changes as delay stages are added or removed to match the delay to the actual cable length. All of these factors can make offset voltage an issue in some applications. To counter the effects of offset, the ISL59920 incorporates a offset compensation circuit that reduces the offset to less than 25mV. An offset correction cycle is triggered by the
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FN6826.0 December 19, 2008
ISL59920
calibration again once the die temperature has settled (20 to 30 seconds after coming out of standby). * After a gain change (X2 pin changes state). The systematic offset is different for a gain of x1 vs. a gain of x2, so an offset calibration is recommended after a gain change. However in a typical application the gain is permanently fixed at x1 or x2, so this is not usually a concern. The DAC level is set through the serial input by bits 1 through 4 directed to the test register (00).
4 INTERNAL DAC SLICING LEVEL
000wxyz
COMPARATORS REDOUT A
Test Pins
Three test pins are provided (Test R, Test G, Test B). During normal operation, the test pins output pulses of current for a duration of the overlap between the inputs, as shown in Figure 15: TESTR pulse = REDOUT (A) with respect to GREENOUT (B) TESTG pulse = GREENOUT with respect to BLUEOUT TESTB pulse = BLUEOUT with respect to REDOUT Averaging the current gives a direct measure of the delay between the two edges. When A precedes B the current pulse is +50A, and the output voltage goes up. When B precedes A, the pulse is -50A. For the logic to work correctly, A and B must have a period of overlap while they are high (a delay longer than the pulse width cannot be measured).
A BLUEOUT A B
TESTR
GREENOUT
A
TESTG B
TESTB B
Signals A and B are derived from the video input by comparing the video signal with a slicing level, which is set by an internal DAC. This enables the delay to be measured either from the rising edges of sync-like signals encoded on top of the video or from a dedicated set-up signal. The outputs can be used to set the correct delays for the signals received.
B
OUTPUT
FIGURE 15. DELAY DETECTOR
Internal DAC Voltage The slice level of the internal DAC may be programmed by writing a byte to the test register (00). Table 3 shows the values that should be written to change the DAC slice level. Please keep in mind when writing to the test register that the LSB should always be zero. Referred to the input, the DAC slice range for the ISL59920 is cut in half for gain of 2 mode because the slicing occurs after the x1/x2 stage output amplifier. (In the EL9115, the slicing occurred before the amplifier so the range of the DAC voltage was the same for either gain of 1 or gain of 2.)
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FN6826.0 December 19, 2008
ISL59920
TABLE 3. DAC VOLTAGE RANGE - INPUT REFERRED wxyz 1000 1001 1010 1011 1100 1101 1110 1111 0000 0001 0010 0011 0100 0101 0110 0111 DAC RANGE [mV] (GAIN 1) -400 -350 -300 -250 -200 -150 -100 -50 0 50 100 150 200 250 300 350 DAC RANGE [mV] (GAIN 2) -200 -175 -150 -125 -100 -75 -50 -25 0 25 50 75 100 125 150 175
Power Dissipation
As the delay setting increases, additional filter blocks turn on and insert into the signal path. When the delay per channel increments, VSP current increases by 0.9mA while VSM does not change significantly. Under the extreme settings, the positive supply current reaches 141mA and the negative supply current can be 41mA. Operating at 5V power supply, the worst-case ISL59920 power dissipation is:
PD = 5 * 141mA + 5 * 41mA = 910mW (EQ. 1)
The minimum JA required for long term reliable operation of the ISL59920 is calculated using Equation 2:
JA = ( T J - T A ) PD = 55 C W (EQ. 2)
Where: TJ is the maximum junction temperature (+135C) TA is the maximum ambient temperature (+85C) For a 20 Ld package on a well laid-out PCB with good connectivity between the QFN's pad and the PCB copper area, 31C/W JA thermal resistance can be achieved. This yields a much higher power dissipation of 3.54W using Equation 2 (see Figure 12). To disperse the heat, the bottom heat spreader must be soldered to the PCB. Heat flows through the heat spreader to the circuit board copper then spreads and convects to air. Thus, the PCB copper plane becomes the heatsink (see TB389). This has proven to be a very effective technique. A separate application note, which details the 20 Ld QFN PCB design considerations, is available.
NOTE: Test Register word = 000wxyz0. wxyz fed to DAC. z is LSB
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FN6826.0 December 19, 2008
ISL59920 Quad Flat No-Lead Plastic Package (QFN)
A N (N-1) (N-2) D B
L20.5x5C
20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220) MILLIMETERS SYMBOL A A1 b c D MIN 0.80 0.00 0.28 NOMINAL 0.90 0.02 0.30 0.20 REF 5.00 BASIC 3.70 REF 5.00 BASIC 3.70 REF 0.65 BASIC 0.35 0.40 20 5 REF 5 REF 0.45 MAX 1.00 0.05 0.32 NOTES 8 8 4 6 5 Rev. 0 6/06
1 2 3
PIN #1 I.D. MARK
E
(2X) 0.075 C (N/2) 0.075 C TOP VIEW
D2 E E2 e L N ND NE
(2X)
C SEATING PLANE
e
0.10 C
0.08 C N LEADS AND EXPOSED PAD
SEE DETAIL "X" SIDE VIEW
NOTES: 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Tiebar view shown is a non-functional feature. 3. Bottom-side pin #1 I.D. is a diepad chamfer as shown. 4. N is the total number of terminals on the device.
0.01 M C A B L N LEADS b (N-2) (N-1) N PIN #1 I.D. 3 1 2 3 (E2)
5. NE is the number of terminals on the "E" side of the package (or Y-direction). 6. ND is the number of terminals on the "D" side of the package (or X-direction). ND = (N/2)-NE. 7. Inward end of terminal may be square or circular in shape with radius (b/2) as shown. 8. If two values are listed, multiple exposed pad options are available. Refer to device-specific datasheet. 9. One of 10 packages in MDP0046
NE 5 (N/2)
(D2) BOTTOM VIEW
7
C
A
(c)
2
A1 DETAIL "X"
(L) N LEADS
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 11
FN6826.0 December 19, 2008

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